Modern mainframe data processing systems include central processing units (CPU), central memory directly addressable by the CPU, input-output (I/O) storage devices to enter data into and record data from the system, and I/O processing systems which control and buffer the movement of data between the I/O devices and the central memory. I/O processing systems relieve the CPU of directly controlling the I/O devices and permit data processing to proceed concurrently with I/O operations.
To permit I/O processing to proceed independently of data processing it is necessary that the central memory be directly addressable by the I/O processing system. Typically, direct addressing is accomplished by the I/O processing system through either sharing a direct memory address (DMA) port with the CPU, or by providing two or more DMA ports and dedicating at least one to the exclusive use of the I/O system. In either case, however, I/O data transfers to and from the central memory are typically limited to only a few, and often only one, central memory access path. The path or paths must be used efficiently, or else data processing speed can be sacrificed, particularly in large or fast data processing systems which require quick reference to large blocks of data scattered throughout a large library maintained in a plurality of peripheral storage devices. Thus to be effective an I/O processing system must not only be able to gain quick access to any one of a considerable number of peripheral devices and any one of many records stored in a particular device, but must also be able to move the data associated with each record to and from the central memory quickly and efficiently.
The above-described requirements for effective I/O processing systems dictate certain aspects of their design. For example, the central memory DMA port or ports must be multiplexed to provide a data channel to and from each peripheral device. This may be accomplished by at least two different techniques, or a combination of the two, one providing a plurality of independent data paths each servicing one peripheral device and hardware multiplexing these paths to the DMA port, or for another providing a shared data path servicing two or more peripheral devices on a time multiplexed basis.
I/O processing systems must also include at least enough intelligence to carry out specific I/O tasks without resort to the mainframe CPU. How much intelligence, and where the intelligence is implemented in the 1/0 system is a matter of great importance to the overall complexity, expense and flexibility of the I/O processing system. Some prior art systems concentrate I/O intelligence in one location and multiplex or distribute control information through one or more control channels to two or more relatively simple peripheral devices, in which case the peripheral devices can perform few, if any, operations independently of the multiplexed intelligence source. Another approach in the prior art has been to provide each peripheral device with relatively high level intelligence so that the devices, once instructed, require little or no supervision in carrying out an I/O function. The former approach has the advantage of centralizing the more expensive and sophisticated intelligence hardware, thus reducing the over system cost, but can limit the response time of peripheral devices controlled therewith, and, can be complicated in its implementation. The latter approach, of course, is more expensive to implement but is simpler in design (as multiplexing needs are reduced reduced or eliminated), but can result in redundant resources in the I/O system.
Another aspect common to most I/O processing systems is data buffering between the central memory DMA port and the peripheral devices. Buffering has several purposes, among them the synchronization of data transfers between the relatively slow peripheral devices and the relatively fast central memory, and the assembling or dissambling of data words as required by the different widths of data paths and the differing organization, i.e. 16-bit, 32-bit, etc. . . . ) of the central memory and peripheral devices. As may be readily appreciated there are a multitude of design possibilities for I/O processing systems using different degrees, types and combinations of multiplexing, intelligence and buffering. The ultimate objective being however in any case the provision of a flexible, efficient, managable, reliable and low cost I/O processing system capable of sustaining a relatively high I/O throughput. Two of the many possibilities may be seen in U.S. Pat. No. 3,432,813--APPARATUS FOR CONTROL OF A PLURALITY OF PERIPHERAL DEVICES--E.J. Annunziata et al, and U.S. Pat. No. 3,725,864--INPUT/OUTPUT CONTROL - Clark et al.
Annunziata et al discloses an I/O processing system in which, generally, a main multiplexing channel is interposed between the CPU (including the central storage or memory) and a plurality of control units each capable of directly controlling several I/O devices such as tape units or disk drives. The main channel provides a plurality of subchannels each for connection to a pair of control units and includes data registers and controls common to the subchannels, and a local storage for storing I/O commands or unit control words to be executed. Four selector subchannels are provided to interface with relatively high speed I/O devices such as "hyperspeed" tape units, and a multiplexer subchannel is provided to interface with relatively slow devices, such as card readers. The operation of one of the selector subchannels begins with the execution of a start I/O instruction by the CPU, which causes the main channel control to retrieve associated unit control words from the central memory and store the same in the local memory. The particular subchannel which interfaces with the I/O device for which the I/O instruction is intended is then activated to interlock with the device via the corresponding control unit. Thereafter, commands are transferred from the local storage to the control unit, which in turn controls the selected I/O device accordingly. In read operations 8-bit bytes are retrieved from the I/O device and assembled in the subchannel to form a 64-bit word. Once a word is assembled, it is immediately transferred to a second register and the subchannel requests access to the central memory for storage thereof. A similar but reverse process is employed in write operations. It should be noted that once a selector subchannel is interlocked with an I/O device it remains so until the entire I/O operation is completed. Thus, no more than four I/O devices may be operating via the selector subchannels at any given time, and only one of the plurality of devices interfaced through each selector subchannel may be accessed at a time. Of course, both of these limitations are less than desirable, and there are others, for instance highly desirable burst transfers of data to and from the central memory cannot be accomplished.
Annunziata's multiplexer subchannel can, however, operate all the peripheral devices attached thereto simultaneously. Peripheral devices connected to the multiplexer subchannel are placed in operation in the same manner as those connected to selector subchannels. However, once an I/O transfer is initiated, the unit control word or words are transferred from the channel back to local memory, whereby the multiplexer subchannel is free to operate other devices until the commanded device requires service, i.e. is ready to accept or produce a byte of data. At that point the unit control word or words are again transferred to the subchannel and the byte is either accepted or produced. In between service periods, the portions of the 64-bit word to be assembled from the peripheral device or dissambled for transfer to the device are stored in local memory. However, while the multiplexer subchannel design is viable for relatively slow devices, it is apparently unsuitable for faster devices, such as disk drive units.
Clark et al discloses an I/O processing system similar to that of Annunziata et al but of a more sophisticated design. For example, Clark et al employs cross point switching between a plurality of control units (each associated with different channels) and a plurality of I/O devices so that any one of the I/O devices may be accessed by any of the channels. This, of course, improves I/O processing flexibility over the system of Annunziata et al. Similarly, Clark et al discloses a system of device-control unit interfacing wherein a single I/O device is selectively interfacable to at least two different control units, which is also an improvement over the system disclosed in Annunziata et al. Aside from improved flexibility of device access through the available channels Clark et al also discloses an improved system for multiplexing channel control capability over time. Briefly, this system somewhat resembles the technique used in Annunziata et al to operate a plurality of slow peripheral devices through a single channel. Clark et al, however, extends that technique so that two or more channels may be multiplexed to service a plurality of devices wherein, for example, a first channel may be employed to initiate an I/O operation in a first peripheral device and then logically disconnected for use in servicing other peripheral devices during the latent period of the first device, and a second channel may be employed to control the first peripheral device when it again requires service.
Thus, the system of Clark et al provides for much greater flexibility in accessing peripheral devices by providing multiple channel access paths to each device and for more efficient utilization of available channel resources. The system is, however, much more complicated than that provided in Annunziata et al, both in terms of interconnection of the various channels, control units and peripheral devices and in terms of the quantity and sophistication of control hardware implemented. Also, Clark et al pays little heed to optimization of data handling both in terms of maximizing available I/O throughput potential and in terms of guaranteeing a short maximum response time to fetch or store data in any given I/O peripheral device.
The present invention, on the other hand, provides a switchless peripheral interface system which both maximizes hardware utilization and guarantees that all peripheral devices interfaced therethrough may be accessed in substantially the same amount of time, such that no peripheral device may monopolize the available I/O channels. Furthermore, I/O capacity is provided such that all peripheral devices may transfer data simultaneously at substantially maximum capacity under typical operating conditions, so that maximum throughput is limited primarily by the number of peripheral devices implemented, and not by available I/O channel resources. In addition, buffering requirements are held to a minimum through three or more stages of synchronized buffers distributed between the peripheral device storage medium and the mainframe CPU, and the pairing of buffers in certain components of the system. Moreover, the peripheral interface system of the present invention employs intelligent control logic in virtually all components of the interface system, with the intelligence being synchronized to operate in a highly coordinated and efficient manner.